The invention relates to electronic data processing, and more specifically concerns speculative translation of register addresses in pipelined data processors.
The performance of data processors, and especially of integrated-circuit microprocessors, increases steadily as clock speed rises and as the size of individual components shrinks, permitting greater architectural complexity.
Most of the instructions in almost every program merely move data from one place to another, rather than actually manipulating it. Therefore, avoiding data transfers has a potential for increasing performance significantly. Microprocessors having modern RISC (reduced instruction set computer), superscalar, and similar architectures have large files of internal registers that most instructions address directly for operands and results. Because these general-purpose architectural registers typically lie on a critical execution path, their speed is very important for overall processor performance.
No matter how many general-purpose registers a processor has, programs always need more. For example, subroutine calls must preserve the state of calling-program registers, yet the called subroutine also uses a full set of registers. Software pipeline looping, sometimes called rotating scheduling, permit virtual unrolling of program loops for faster execution in superscalar processors. This feature presents a more recent requirement for large numbers of quickly switchable registers.
One way to avoid impossibly large numbers of registers while avoiding the delay of moving data from one register to another is to leave the data where it is and change the effective addresses of the registers. That is, renaming a register can be faster than moving its contents to another register having the proper fixed address. However, sophisticated renaming algorithms become complex, and some must vary the address mappings on an instruction-by-instruction basis. Therefore, the translation that implements the renaming operation requires high speed and efficiency, including quick turn-around for register-mapping changes.
The invention providess a pipelined data processor having instructions at different stages of execution. Some of the instructions specify virtual addresses into a file of registers having physical addresses. A speculative translator maps the virtual registers of an instruction at one pipeline stage into physical addresses for speculative use by the instruction at a later pipeline stage.